Responsibilities
Architecting the company’s next-gen networking ASIC devices;
Drive ASIC performance, power, area scheduling, modeling, and analysis and track through the entire design flow;
Responsible for chip level specification authoring, C model development, architectural validation plan, and execution;
Review all blocks’ microarchitecture specifications and software development to ensure all system architectural requirements are followed;
Tracking relevant industry standards and IP technical evaluation.

Qualifications
10+ years of complex high-speed digital IC architecture experience;
Master’s degree in Electrical Engineering or Computer Engineer or related field required; Ph.D. degree a plus;
Strong working knowledge of System C or C++, or relevant programming language;
Excellent knowledge of ARM subsystem, PCIe and industry standard peripherals including I2C, UART, SPI;
Experiences with complex networking ASIC architecture and knowledge with networking protocols and RFCs are big plusses.

Compensations
We offer very competitive salary, significant stock equity, and generous benefits plan.

Working Locations
Shanghai Zhangjiang or Shenzhen Nanshan.