Responsibilities
Establishing and leading a high-performing team of ASIC design engineers to build the company’s next-gen networking ASIC devices;
Responsible for all the aspects of the ASIC front end design, including the micro-architecture, RTL, synthesis, logic and timing verification;
Document, execute the plan, and deliver fully verified, high performance, area and power efficient design to achieve the targets and specifications;
Work with the verification team, guide and review the verification plan;
Participate in post silicon bring-up and validation.

Qualifications
15+ years of complex high-speed digital IC design experience with all stages in the ASIC design flow including emulation, prototyping, DFT, Synthesis, timing analysis, floorplanning, ECO, bringup & lab debug, and ATE test development;
Proven track record of managing IC design teams with multiple successful complex ASIC tape-outs in a highly dynamic environment;
Master’s degree in Electrical Engineering or Computer Engineer or related field required; Ph.D. degree a plus;
Experience with standard EDA tools from Synopsys or Cadence;
Strong working knowledge of languages relevant to the ASIC development process including Verilog, Unix/Perl Scripting or Python, and C/C++;
Excellent knowledge of ARM subsystem, PCIe and industry standard peripherals including I2C, UART, SPI;
Experiences with complex networking ASIC design and knowledge with networking protocols and RFCs are big plusses.

Compensations
We offer very competitive salary, significant stock equity, and generous benefits plan.



Working Locations
Shanghai Zhangjiang or Shenzhen Nanshan.