Responsibilities
Establishing and leading a high-performing team of ASIC design verification engineers to verify the company’s next-gen networking ASIC devices;
Responsible for all the aspects of the ASIC design verification - formulating the verification strategy, building the state-of-art testbench, developing the detailed test plan and test cases, carrying out the regression and tracking the status, driving the coverage closure, and executing the emulation plan;
Work closely with architecture and design teams to deliver a fully verified design to achieve bug-free tapeout;
Participate in post silicon bring-up and validation.

Qualifications
15+ years of complex high-speed digital IC design verification experience with all stages in the ASIC design verification flow;
Proven track record of managing IC design verification teams with multiple successful complex ASIC tape-outs in a highly dynamic environment;
Master’s degree in Electrical Engineering or Computer Engineer or related field required; Ph.D. degree a plus;
Strong working knowledge of Verilog, SystemVerilog, UVM, Scripting language (Perl);
Experience with standard EDA tools from Synopsys or Cadence;
Familiar with advanced verification methodologies;
Experiences with complex networking ASIC design verification, knowledge with networking protocols and RFCs, and experience with emulation platforms (Synopsys Zebu or Cadence Palladium) are big plusses.

Compensations
We offer very competitive salary, significant stock equity, and generous benefits plan.

Working Locations
Shanghai Zhangjiang or Shenzhen Nanshan.